Design Space Exploration of Network-on-Chip at System level
Jena, Rabindra Kumar![Design Space Exploration of Network-on-Chip at System level](https://support.digitalhusky.com/media/annotations/sorted/123/12311774/CHSBZCOP0312311774.jpg)
About the Book: The goal of this text is to help students, researchers and academicians, who are working in the field of CAD for VLSI. Network-on-Chip(NoC) has been recently developed as an on-chip communication solution for System-on-Chip(SoC) design. This paradigm supports various communication resources at a time and overcomes the limitations of bus-based System. Design space exploration methodology at system level reduces the time-to-marke...