Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
Pineda de Gyvez, José / Sachdev, Manoj![Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits](https://support.digitalhusky.com/media/annotations/sorted/253/2534081/CHSBZCOP032534081.jpg)
Failures of nano-metric technologies owing to defects and shrinking process tolerances give rise to significant challenges for IC testing. As the variation of fundamental parameters such as channel length, threshold voltage, thin oxide thickness and interconnect dimensions goes well beyond acceptable limits, new test methodologies and a deeper insight into the physics of defect-fault mappings are needed. In Defect-Oriented Testing for Nano-Met...