Cache and Interconnect Architectures in Multiprocessors
Thakkar, Shreekant S. / Dubois, Michel![Cache and Interconnect Architectures in Multiprocessors](https://support.digitalhusky.com/media/annotations/sorted/154/15467437/CHSBZCOP0315467437.jpg)
Cache And Interconnect Architectures In Multiprocessors Eilat, Israel May 25-261989 Michel Dubois UniversityofSouthernCalifornia Shreekant S. Thakkar SequentComputerSystems The aim of the workshop was to bring together researchers working on cache coherence protocols for shared-memory multiprocessors with various interconnect architectures. Shared-memory multiprocessors have become viable systems for many applications. Bus based shared-memory...