Due to increase in device density and battery-powered devices, the power density increases substantially. Digital designs nowadays often adopt intensive pipe lining techniques and employ many flip-flop rich modules such as register files, shift registers and FIFO. For big circuits implementing complex functionalities like control units, microprocessors etc, a very large number of flip-flops are used. So these flip-flops heavily affect the power and performance of the entire system. Therefore the power consumption of such circuits must be reduced without weakening other characteristics. This book begins with the factors that can be reduced to optimize the power dissipation. Different types of clocked storage elements are reviewed in this book. Different state-of-the-art master slave double edge triggered flip-flops (DETFFs) are reviewed and implemented on TSPICE using BSIM models. The nominal simulation conditions, along with analysis and optimization performed during simulation, are discussed. In this book, simulation results of double edge triggered flip-flops are presented and performances of the designs are compared in terms of power, delay, PDP and transistor count.