A tool flow is presented for deriving acceleratorcircuits on an FPGA from ANSI C source code by exploring architecturesolutions that conform to a preset template through scheduling andmapping algorithms. A case study carried out on simulatedannealing-based scheduling software used for spacecraft systems isexplained. The goal of the tool is the derivation of a design thatmaximizes throughput while minimizing footprint. Results obtained arecompared with a peer C to RTL tool, a space-borne embedded processor and acommoditydesktop processor for a variety of problems.
Lieferbar
ISBN | 9783639165128 |
---|---|
Sprache | eng |
Cover | Kartonierter Einband (Kt) |
Verlag | VDM Verlag |
Jahr | 2009 |
Dieser Artikel hat noch keine Bewertungen.